Physical RAM & Memory Allocation Lab
Interactive evaluation of contiguous address arithmetic (Base + offset) and geometric dynamic capacity doubling ($2 \to 4 \to 8 \to 16$).
Hardware Architecture Engine
Contiguous RAM Layout & O(1) Pointer Arithmetic
CPU Memory Management Unit (MMU) Calculation:Latency: 1 Clock Cycle (0.3ns)
Address(arr[2]) = 0x1000 + (2 × 4 bytes) = 0x1008
The CPU hardware executes a single LEA (Load Effective Address) opcode to compute the memory address without scanning preceding elements.
Memory Management Engine
Dynamic Array Capacity Doubling & Amortized O(1)
Contiguous Buffer in Virtual Memory:Amortized Push: O(1)
[0]
10
[1]
20
Allocation Engine Log:
Dynamic array initialized with size: 2, capacity: 2.